Open Source Verilog HDL Synthesis with Yosys


Vortragender Clifford Wolf
Ort Metalab, Rathausstraße 6, 1010 Wien
Datum 2014-12-04
Zeit 19:00

Yosys is the first full-featured open source software for Verilog HDL synthesis. It supports most of Verilog-2005 and is well tested with real-world designs from the ASIC and FPGA world.

Learn how to use Yosys to create your own custom synthesis flows and discover why open source HDL synthesis is important for researchers, hobbyists, educators and engineers alike.

This presentation covers basic concepts of Yosys, writing synthesis scripts for a wide range of applications, creating Yosys scripts for various non-synthesis applications (such as formal equivialence checking) and writing extensions to Yosys using the C++ API.

(Copy&Paste von bestehender Beschreibung. Vortrag Deutsch, Folien Englisch.)